Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce low-power nano-scale embedded and Internet Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based half adder (THA) multiplier (TMUL) use novel unary operator implement two power supplies Vdd Vdd/2 without using any decoders, basic gates, or encoders minimize the number used transistors improve efficiency. Extensive simulations (over 160) proposed designs PVT (Process, Voltage, Temperature) variations, noise effect, scalability studies, along with several benchmark HSPICE simulator, prove significance decrease power-delay product (PDP), robustness process tolerance. obtained results show superiority a reduction between 32% 74% count 18% 99% PDP compared most recent works.